Physical Design – Expert/Manager/Consultant






  • Lead backend team to complete SOC and FPGA physical design on time with quality
  • Timing and power signoff of FPGA core fabric and SOC chips
  • Optimize backend flow for FPGA core, such as top floor plan, P&R and signoff scripts
  • Build automation flow of top-level clock tree design for big chips
  • Research of physical design methodology for future product
  • Train and guide relative junior team members
  • Documentation of backend spec, report and lesson learning


  • B.S with 10+ years of experience or MS with 8+ years of experiences on physical design
  • Signoff experiences and successful track records of taping out chips with over 100 million gates
  • Strong background of power rail design and related EM/IR-Drop/crosstalk analyzing
  • Experiences of SDC, timing analyzing, timing/noise violation fixing and CTS
  • Hand-on skills of EDA tools, such as Design Compiler, Innovus, ICC2, Calibre, Primetime, StarRC etc.


*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status